International Journal / Conference
2025
2024
Munhyung Lee, Taehan Lee, Junwon Yeo and Hyukjun Lee
“Enhancing On-device DNN Inference Performance with a Reduced Retention-Time MRAM-Based Memory Architecture”
IEEE Access, Nov 2024
Munhyung Lee, Taehan Lee, Junwon Yeo and Hyukjun Lee
“Enhancing Performance of Deep Neural Networks with a Reduced Retention-Time MRAM-Based Memory Architecture”
61th Design Automation Conference (DAC’24), Work-in-Progress (WIP) Poster Sessions, San Francisco, USA, June 23-27, 2024
2023
Yongwoon Song, Munhyung Lee and Hyukjun Lee,
“High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM,”
IEEE Access, Sep 2023
2022
Jeongbin Kim, Yongwoon Song, Kyungseon Cho, Hyukjun Lee, Hongil Yoon and Eui-Young Chung,
“STT-MRAM based Multi-Context FPGA for Multithreading Computing Environment,”
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, May 2022
2021
Yongwoon Song, Jooyoung Hwang, Insoon Jo, and Hyukjun Lee,
“Highly Available Packet Buffer Design with Hybrid Non-volatile Memory,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, Oct. 2021
2020
Chungseop Lee, Keonhyuk Lee, Mingoo Kang, and Hyukjun Lee,
“EANeM: Energy-Aware Network Stack Management for Mobile Devices,”
57th Design Automation Conference (DAC’20), San Francisco, USA, July 19-23, 2020
Minsik Oh, Kwangsu Kim, Duheon Choi, Hyukjun Lee, and Eui-Young Chung,
“Per-Operation Reusability based Allocation and Migration Policy for Hybrid Cache,
IEEE Transactions on Computers , Volume: 69, Issue: 2, Feb. 1 2020
2019
Bobae Kim and Hyukjun Lee,
“IP-aware Cache Partition and Replacement Scheme for Mobile Computing Devices”
IEICE Electronics Express, Volume 16 Issue 15, 2019
Yongwoon Song, Dongkeon Choi, and Hyukjun Lee,
“Designing a High Performance SRAM-DRAM Hybrid Memory Architecture for Packet Buffers,”
IEICE Transactions on Electronics, 2019
Myeongjin Kim, Wontaeck Jung, Hyuk-Jun Lee, and Eui-Young Chung,
“A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
2018
Chinam Kim, and Hyukjun Lee,
“A High-Bandwidth PCM-based Memory System for Highly Available IP Routing Table Lookup,
IEEE Computer Architecture Letters, Volume: 17 , Issue: 2 2018 (SCIE)
Hyunwoo Park, Hyun So, and Hyukjun Lee,
“Application Specific Cache Design Using STT-RAM Based Block-RAM for FPGA-Based Soft Processors,”
IEICE Electronics Express, Vol. 15 , Issue 10, 2018 (SCIE)
Yoojin Kim, Yongwoon Song, and Hyukjun Lee,
“Energy efficient mobile positioning system using adaptive particle filter,”
IEICE Transactions on Fundamentals, Volume and Number: Vol.E101-A,No.6,pp.-,Jun. 2018, (SCIE)
2017
Taehyun Kim, Jongbum Lim, Jinku Kim, Woo-Cheol Cho, Eui-Young Chung and Hyukjun Lee
“Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors,”
ACM Transactions on Design Automation of Electronic Systems, Vol. 22, No. 4, Article 59, 2017
Junghee Lee, Kalidas Ganesh, Hyuk-Jun Lee, and Youngjae Kim,
“FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory,”
IEEE Computer Architecture Letters, 16(2):115-118, 2017, (SCIE)
2016
Jin-ku Kim, Jong-bum Lim, Woo-cheol Cho, Kwang-Sik Shin, Hoshik Kim and Hyuk-Jun Lee,
“Adaptive Memory Controller for High-Performance Multi-channel Memory,”
Journal of Semiconductor Technology and Science, Vol.16 No.6, 2016.12, 808-816, (SCIE)
Jin-Ku Kim and Hyuk-Jun Lee,
“IP Deadline-Aware Bank Partition Scheme for Memory Scheduler in Mobile Platform,”
1st International Conference on Consumer Electronics(ICCE) Asia, 2016
2015
Seungjoo Son, Hyun So, Joondong Kim, Dongkeon Choi, and Hyuk-Jun Lee,
“Energy-efficient adaptive optical character recognition for wearable devices,”
IET Electronics Letters, vol. 52, Issue 2, pp. 113-115, Jan. 2016. (SCI)
Junyeol Lee, Taehyun Kim, Woo-cheol Cho, and Hyuk-jun Lee,
“Lightweight built-in network monitor in Linux kernel for self-adaptive IoT devices,”
17th International Conference on Advanced Communication Technology (ICACT), 2015
2014
Jongbum Lim, Yongwoon Song, and Hyuk-Jun Lee,
“An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture,”
IEICE Electronics Express, vol. 11, No.19, pp. 20140755-20140755, Sep. 2014. (SCIE)
Sang-Hoon Park, Dong-gun Kim, Kwanhu Bang, Hyuk-Jun Lee, Sungjoo Yoo, and Eui-Young Chung,
“An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices,”
IEEE Transactions on Computers, vol. 63, issue 5, pp. 1085-1096, May 2014. (SCI)
Seunghak Yu, Sungroh Yoon, Eui-Young Chung, and Hyuk-Jun Lee,
“Design of a bitmap-based QoS-aware memory controller for a packet memory,”
IEICE Electronics Express, Vol.11, No.5, pp. 1-12, Mar. 2014. (SCIE)
2013
Kwanhu Bang, Dong-Gun Kim, Sang-Hoon Park, Eui-Young Chung, and Hyuk-Jun Lee,
“Application-aware design parameter exploration of NAND flash memory,”
Journal of Semiconductor Technology and Science, vol. 13, no. 4, pp. 291-302, Aug. 2013. (SCIE)
Samkyu Won, Eui-Young Chung, Duckju Kim, Junseop Chung, Bongseok Han, and Hyukjun Lee,
“Page overwriting method for performance improvement of NAND flash memories,”
IEICE Electronics Express, vol. 10, no. 6, pp. 1-6, 2013. (SCIE)
Sang Guun Yoo, Hyukjun Lee and Juho Kim,
“A Performance and Usability Aware Secure Two-factor User Authentication Scheme for Wireless Sensor Networks,”
International Journal of Distributed Sensor Networks, 2013. (SCIE)
Hyuk-Jun Lee, Seung-Chul Kim, and Eui-Young Chung,
“A low-power packet memory architecture with a latency-aware packet mapping method,”
IEICE Transactions on Information and Systems, vol. E96-D, no. 4, pp. 963-966, Apr. 2013. (SCIE)
Dae-Young Jung, Hyuk-Jun Lee, Sung-Yong Park, Myoung-Wan Koo, Ji-Hwan Kim, Jeong-sik Park, Hyung-Bae Jeon, and Yun-Keun Lee,
“Implementation of a Large-scale Language Model in a Cloud Environment for Human-Robot Interaction,”
3rd International Conference on Intelligent Robotics, Automations, Telecommunication facilities, and Applications (IRoA), 2013
SeungCheol Kim, Sae Hyong Park, Yongwoon Song, Woocheol Cho, and Hyuk-Jun Lee,
“Application-aware Optimization of Networking Protocols for Data Centers,”
15th International Conference on Advanced Communication Technology (ICACT), 2013
2012
Hyun-Jun Lee, Woo-Cheol Cho, and Eui-Young Chung,
“Analytical memory bandwidth model for many-core processor based system,”
IEICE Electronics Express, vol. 9, no. 18, pp. 1461-1466, 2012. (SCIE)
Hyuk-Jun Lee, Seung-Cheol Kim, and Eui-Young Chung,
“Fast Correction of Multiple Soft Errors in Highly Associative Cache with CAM-based Tag,”
COMMUNICATIONS IN COMPUTER AND INFORMATION SCIENCE (SCOPUS), vol. 339, pp. 424-431, 2012.
Kwonyong Lee, Sungyong Park, and Hyuk-Jun Lee,
“Improving MapReduce Performance using Block Device Reconfiguration in Virtualized Clouds,”
Advanced Researches on Software Technology (ASTL), 2012
Before 2011
Hyuk-Jun Lee, and Eui-Youn Chung,
“Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory,”
IEEE Transactions on Very Large Scale Integration Systems, vol. 16, issue. 3, 2008. (SCIE)
Hyuk-Jun Lee,
“Immediate soft error detection using pass gate logic for content addressable memory,”
Electronics Letters, vol. 44, issue. 4, 2008. (SCI)
Eui-Young Chung, Hyuk-Jun Lee, and Sung Woo Chung,
“Scenario-aware Bus Functional Modeling for Architecture-level Performance Analysis,”
IEICE Transactions on Fundamentals, vol. E90-A, no. 4, pp. 875-878, Apr. 2007. (SCIE)
Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, and Eui-Young Chung,
“Latency-Aware Bus Arbitration for Real-Time Embedded Systems,”
IEICE Transactions on Information and Systems, vol. E90-D, no. 3, pp. 676-679, Mar. 2007. (SCIE)
M Jun, K Bang, HJ Lee, N Chang, and EY Chung,
“Slack-based bus arbitration scheme for soft real-time constrained embedded systems,”
Design Automation Conference (DAC), pp. 159-164, 2007
HJ Lee, and MJ Flynn,
“High-speed interconnect schemes for a pipelined FPGA,”
IEEE Proceedings-Computers and Digital Techniques, vol. 147, issue. 3, pp. 195-202, 2000. (SCIE)
HJ Lee, and MJ Flynn,
“Coarse-grained carry architecture for FPGA (poster abstract),”
ACM/SIGDA 8th International Symposium on Field Programmable Gate Array (FPGA), 2000
Domestic Journal / Conference
이우진, 서동휘, 이혁준
“AST 모델에 대한 양자화 기법 적용 및 성능 분석”
한국소프트웨어종합학술대회, 2024
이태한, 류지성, 이혁준
“MCU에서의 시계열 분류를 위한 DNN 구조 탐색”
임베디드공학회 추계학술대회, 2023
강태호, 이혁준
“TSC-NAS 임베디드 시스템 내 센서 데이터의 On-Device 학습을 위한 신경망 구조 탐색 알고리즘”
정보과학회 학술 논문집 : p. 954-956, 2022
이문형, 윤다영, 이혁준
“사물인터넷기기에서의 심층 인공신경망 응용의 효과적인 메모리 사용을 위한 인공신경망 탐색”
정보과학회 학술 논문집 : p. 1589-1591, 2022
조용우, 한규수, 이혁준,
“자소 단위 기반의 양방향 LSTM-CNN을 활용한 영화 평점 예측”
정보과학회 학술논문집 : p. 1009-1011, 2018
박현우, 이혁준,
“FPGA의 기억 소자를 휘발성에서 비휘발성 메모리로 대체 시 최적의 architectural parameter 변화에 대한 연구”
정보과학회 학술논문집 : p. 1311-1313, 2016
손승주, 최동건, 임종범, 송용운, 이혁준,
“웨어러블 컴퓨터를 위한 문자 인식 성능 측정”
정보과학회 학술논문집 : p. 1509-1511, 2014
이혁준,
“매니 코어 기반 패킷 프로세서 디자인 이슈“
정보과학회논문지 : 시스템 및 이론 (40권, 2호) , 1229-6- 83X, 2013
이명현, 이세일, 이혁준, 윤성로,
“ONFI 최적화 낸드컨트롤러 구현 및 성능 분석”
정보과학회논문지 : 컴퓨팅의레터 (19 권, 3호), 1229-7-712, 2013
방관후, 박상훈, 이혁준, 정의영,
“논리 블록의 접근경향을 활용한 이종 낸드 플래시 기반 저장장치를 위한 Flash Translation Layer”
전자공학회논문지 (50권, 5호), 1229-5-026, 2013
방관후, 박상훈, 이혁준, 정의영,
“캐시 버퍼와 읽기 요청을 고려한 낸드 플래시 기반 솔리드 스테이트 디스크의 요청 스케줄링 기법”
전자공학회논문지 (50권, 8호) , 1229-5-026, 2013
Patents
| 특허상태 | 발명인 | 출원명 / 출원 및 등록 번호 |
| 등록 | 이혁준, 소현 | 컨볼루션 신경망 기반의 입력 분류 장치 및 방법 10-2018-0132656 / 10-2533235 |
| 등록 | 이혁준, 강태호, 이문형 | 임베디드 기기 내 센서데이터의 온-디바이스 학습을 위한 신경망 구조 탐색방법 10-2022-0184786 / 10-2567024 |
| 출원 | 이혁준, 송용운 | 네트워크 장비용 비휘발성 복합 메모리 및 비휘발성 복합 메모리 동작 방법 10-2022-0028700 |
| 등록 | 이혁준, 김지남 | 라우팅 테이블 검색 방법 및 이를 구현하는 메모리 시스템 10-2019-0024774 / 10-2101419 |
| 출원 | 이혁준 | 캐시 메모리 장치 및 이를 포함하는 FPGA 10-2017-0174713 |