International Journal | Domestic Journal | International Conference | Domestic Conference



Hyunwoo Park, Hyun So, and Hyukjun Lee,
“Application Specific Cache Design Using STT-RAM Based Block-RAM for FPGA-Based Soft Processors,”
IEICE Electronics Express, Accepted, (SCIE)


Yoojin Kim, Yongwoon Song, and Hyukjun Lee,
“Energy efficient mobile positioning system using adaptive particle filter,”
IEICE Transactions on Fundamentals, Volume and Number: Vol.E101-A,No.6,pp.-,Jun. 2018, (SCIE) , Accepted




Tae-Hyun Kim, Jong-bum Lim, Jin-ku Kim, Woo-cheol Cho, Eui-Yong Chung, and Hyuk-Jun Lee,
“Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Many-core Based Network Processors,”
ACM Transactions on Design Automation of Electronic Systems , Accepted, (SCIE)


Junghee Lee, Kalidas Ganesh, Hyuk-Jun Lee, Youngjae Kim,
“FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory,”
IEEE Computer Architecture Letters, 16(2):115-118, 2017, (SCIE) , Accepted





Jin-ku Kim, Jong-bum Lim, Woo-cheol Cho, Kwang-Sik Shin, Hoshik Kim and Hyuk-Jun Lee,
“Adaptive Memory Controller for High-Performance Multi-channel Memory,”
Journal of Semiconductor Technology and Science, Vol.16 No.6, 2016.12, 808-816, (SCIE)




Seungjoo Son, Hyun So, Joondong Kim, Dongkeon Choi, and Hyuk-Jun Lee,
“Energy-efficient adaptive optical character recognition for wearable devices,”
IET Electronics Letters, vol. 52, Issue 2, pp. 113-115, Jan. 2016. (SCI)




Jongbum Lim, Yongwoon Song, and Hyuk-Jun Lee,
“An optimal DRAM sizing and partitioning method for NVRAM based hybrid memory architecture,”
IEICE Electronics Express, vol. 11, No.19, pp. 20140755-20140755, Sep. 2014. (SCIE)


Sang-Hoon Park, Dong-gun Kim, Kwanhu Bang, Hyuk-Jun Lee, Sungjoo Yoo, and Eui-Young Chung,
“An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices,”
IEEE Transactions on Computers, vol. 63, issue 5, pp. 1085-1096, May 2014. (SCI)


Seunghak Yu, Sungroh Yoon, Eui-Young Chung, and Hyuk-Jun Lee,
“Design of a bitmap-based QoS-aware memory controller for a packet memory,”
IEICE Electronics Express, Vol.11, No.5, pp. 1-12, Mar. 2014. (SCIE)




Kwanhu Bang, Dong-Gun Kim, Sang-Hoon Park, Eui-Young Chung, and Hyuk-Jun Lee,
“Application-aware design parameter exploration of NAND flash memory,”
Journal of Semiconductor Technology and Science, vol. 13, no. 4, pp. 291-302, Aug. 2013. (SCIE)


Samkyu Won, Eui-Young Chung, Duckju Kim, Junseop Chung, Bongseok Han, and Hyukjun Lee,
“Page overwriting method for performance improvement of NAND flash memories,”
IEICE Electronics Express, vol. 10, no. 6, pp. 1-6, 2013. (SCIE)


Sang Guun Yoo, Hyukjun Lee and Juho Kim,
“A Performance and Usability Aware Secure Two-factor User Authentication Scheme for Wireless Sensor Networks,”
International Journal of Distributed Sensor Networks, 2013. (SCIE)


Hyuk-Jun Lee, Seung-Chul Kim, and Eui-Young Chung,
“A low-power packet memory architecture with a latency-aware packet mapping method,”
IEICE Transactions on Information and Systems, vol. E96-D, no. 4, pp. 963-966, Apr. 2013. (SCIE)




Hyun-Jun Lee, Woo-Cheol Cho, and Eui-Young Chung,
“Analytical memory bandwidth model for many-core processor based system,”
IEICE Electronics Express, vol. 9, no. 18, pp. 1461-1466, 2012. (SCIE)


Hyuk-Jun Lee, Seung-Cheol Kim, and Eui-Young Chung,
“Fast Correction of Multiple Soft Errors in Highly Associative Cache with CAM-based Tag,”



Before 2011


Hyuk-Jun Lee, and Eui-Youn Chung,
“Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory,”
IEEE Transactions on Very Large Scale Integration Systems, vol. 16, issue. 3, 2008. (SCIE)


Hyuk-Jun Lee,
“Immediate soft error detection using pass gate logic for content addressable memory,”
Electronics Letters, vol. 44, issue. 4, 2008. (SCI)


Eui-Young Chung, Hyuk-Jun Lee, and Sung Woo Chung,
“Scenario-aware Bus Functional Modeling for Architecture-level Performance Analysis,”
IEICE Transactions on Fundamentals, vol. E90-A, no. 4, pp. 875-878, Apr. 2007. (SCIE)


Minje Jun, Kwanhu Bang, Hyuk-Jun Lee, and Eui-Young Chung,
“Latency-Aware Bus Arbitration for Real-Time Embedded Systems,”
IEICE Transactions on Information and Systems, vol. E90-D, no. 3, pp. 676-679, Mar. 2007. (SCIE)


HJ Lee, and MJ Flynn,
“High-speed interconnect schemes for a pipelined FPGA,”
IEEE Proceedings-Computers and Digital Techniques, vol. 147, issue. 3, pp. 195-202, 2000. (SCIE)